--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:   11:29:08 03/25/2009
-- Design Name:   clock
-- Module Name:   N:/Coursework/DigitalSystemS2/stopwatch/vhdl/counter_testbench.vhd
-- Project Name:  vhdl
-- Target Device:  
-- Tool versions:  
-- Description:  
--
-- VHDL Test Bench Created by ISE for module: clock
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY counter_testbench_vhd IS
END counter_testbench_vhd;

ARCHITECTURE behavior OF counter_testbench_vhd IS

    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT clock
    PORT(
        clockSource : IN std_logic;
        reset : IN std_logic;          
        digit : OUT std_logic_vector(3 downto 0)
        );
    END COMPONENT;

    --Inputs
    SIGNAL clockSource :  std_logic := '0';
    SIGNAL reset :  std_logic := '0';

    --Outputs
    SIGNAL digit :  std_logic_vector(3 downto 0);

BEGIN

    -- Instantiate the Unit Under Test (UUT)
    uut: clock PORT MAP(
        clockSource => clockSource,
        reset => reset,
        digit => digit
    );

    setup : PROCESS
    BEGIN
        reset <= '0';
        wait for 3 ns;
        reset <= '1';
        wait for 3 ns;
        reset <= '0';
        wait;
    END PROCESS;
   
    generateFreq : PROCESS
    BEGIN
         loop
            clockSource <= '0';
            wait for 1.25 ms;
            clockSource <= '1';
            wait for 1.25 ms;
            clockSource <= '0';
        end loop;
        wait;
    END PROCESS;

END;