CodeWiki: DigitalSystems.CW2.VHDL

Revision [376]

Most recent edit made on 2009-05-01 14:43:29 by cmantito [counts & outputs, handshakes with micro. works.]

Additions:

Port ( clockSource : in STD_LOGIC; -- clock pulse from micro

reset : in STD_LOGIC; -- reset pulse from micro
microAck : in STD_LOGIC; -- acknowledgement from micro

digit : out STD_LOGIC_VECTOR (3 downto 0);

-- numbers to micro

cpldRts : out STD_LOGIC); -- ready to send to micro (ACTIVE LOW)

signal controlFlag : std_logic_vector(1 downto 0);
begin

controlFlag <= "10";
cpldRts <= '1';

elsif microAck = '1' then

cpldRts <= '1';

if controlFlag = "00" then

controlFlag <= "01";
cpldRts <= '0';

elsif controlFlag = "01" then

controlFlag <= "10";
cpldRts <= '0';

elsif controlFlag = "10" then

digit <= secondCount;
controlFlag <= "11";
cpldRts <= '0';

elsif controlFlag = "11" then

digit <= tenSecCount;
controlFlag <= "00";
cpldRts <= '0';

hunthsCount <= "0000";

end if;

Deletions:

Port ( clockSource : in STD_LOGIC;

reset : in STD_LOGIC;
digit : out STD_LOGIC_VECTOR (3 downto 0));

signal pulseCount: std_logic_vector(1 downto 0);

pulseCount <= "00";
--if pulseCount = "11" then
hunthsCount <= "0000";
-- pulseCount <= "00";
-- digit <= tenSecCount;

--elsif pulseCount = "00" then
-- pulseCount <= pulseCount + "1";
--elsif pulseCount = "01" then
-- pulseCount <= pulseCount + "1";
--elsif pulseCount = "10" then

digit <= secondCount;

-- pulseCount <= pulseCount + "1";
--end if;

Revision [370]

Edited on 2009-04-01 12:11:09 by cmantito [VHDL in a test mode to count/disp secs only. This seems to work.]

Additions:

--if pulseCount = "11" then
hunthsCount <= "0000";
-- pulseCount <= "00";
-- digit <= tenSecCount;

--elsif pulseCount = "00" then
-- pulseCount <= pulseCount + "1";
--elsif pulseCount = "01" then
-- pulseCount <= pulseCount + "1";
--elsif pulseCount = "10" then
-- pulseCount <= pulseCount + "1";
--end if;

Deletions:

if pulseCount = "11" then

hunthsCount <= "0000";

pulseCount <= "00";
digit <= tenSecCount;

elsif pulseCount = "00" then

pulseCount <= pulseCount + "1";

elsif pulseCount = "01" then

pulseCount <= pulseCount + "1";

elsif pulseCount = "10" then

pulseCount <= pulseCount + "1";

end if;

Revision [366]

Edited on 2009-03-25 12:13:25 by cmantito

Additions:

Deletions:

Revision [364]

Edited on 2009-03-25 12:10:06 by cmantito [confused ' with " RE bits. pulseCount had too many bits. simulates OK.]

Additions:

digit : out STD_LOGIC_VECTOR (3 downto 0));

signal pulseCount: std_logic_vector(1 downto 0);

pulseCount <= "00";
if pulseCount = "11" then

pulseCount <= "00";

elsif pulseCount = "00" then
elsif pulseCount = "01" then
elsif pulseCount = "10" then

end process;

Deletions:

digit : out STD_LOGIC_VECTOR (3 downto 0);

signal pulseCount: std_logic_vector(2 downto 0);

pulseCount <= "0000";
if pulseCount = '100' then

pulseCount <= "000";

elsif pulseCount = '001' then
elsif pulseCount = '010' then
elsif pulseCount = '011' then

Revision [361]

Edited on 2009-03-18 13:50:21 by cmantito [initial commit!]

Additions:

-- Company:
-- Engineer:
--
-- Create Date: 12:25:53 03/18/2009
-- Design Name:
-- Module Name: clock - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Uncomment the following library declaration if instantiating

any Xilinx primitives in this code. --library UNISIM;
--use UNISIM.VComponents.all;

entity clock is

Port ( clockSource : in STD_LOGIC;

reset : in STD_LOGIC;
digit : out STD_LOGIC_VECTOR (3 downto 0);

end clock;

architecture Behavioral of clock is

signal hunthsCount : std_logic_vector(3 downto 0);
signal tenthsCount : std_logic_vector(3 downto 0);
signal secondCount : std_logic_vector(3 downto 0);
signal tenSecCount : std_logic_vector(3 downto 0);
signal pulseCount: std_logic_vector(2 downto 0);
process(reset, clockSource)

begin

if reset = '1' then

hunthsCount <= "0000";
tenthsCount <= "0000";
secondCount <= "0000";
tenSecCount <= "0000";
pulseCount <= "0000";

elsif clockSource'event and clockSource = '1' then

if pulseCount = '100' then

if hunthsCount <= "1000" then

hunthsCount <= hunthsCount + "1";

else

hunthsCount <= "0000";

if tenthsCount <= "1000" then

tenthsCount <= tenthsCount + "1";

else

tenthscount <= "0000";

if secondCount <= "1000" then

secondCount <= secondCount + "1";

else

secondCount <= "0000";

if tenSecCount <= "1000" then

tenSecCount <= tenSecCount + "1";

else

tenSecCount <= "0000";

end if;

end if;

pulseCount <= "000";
digit <= tenSecCount;

elsif pulseCount = '001' then

digit <= hunthsCount;
pulseCount <= pulseCount + "1";

elsif pulseCount = '010' then

digit <= tenthsCount;
pulseCount <= pulseCount + "1";

elsif pulseCount = '011' then

digit <= secondCount;
pulseCount <= pulseCount + "1";

end if;

end if;

end Behavioral;

Revision [360]

Edited on 2009-03-18 11:46:58 by cmantito

Additions:

Revision [359]

The oldest known version of this page was edited on 2009-03-18 11:46:47 by cmantito [create]

See also: DigitalSystems.CW2
Categories: CategoryUni