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-- Company:
-- Engineer:
--
-- Create Date: 12:25:53 03/18/2009
-- Design Name:
-- Module Name: clock - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clock is
Port ( clockSource : in STD_LOGIC; -- clock pulse from micro
reset : in STD_LOGIC; -- reset pulse from micro
microAck : in STD_LOGIC; -- acknowledgement from micro
digit : out STD_LOGIC_VECTOR (3 downto 0);
-- numbers to micro
cpldRts : out STD_LOGIC); -- ready to send to micro (ACTIVE LOW)
end clock;
architecture Behavioral of clock is
signal hunthsCount : std_logic_vector(3 downto 0);
signal tenthsCount : std_logic_vector(3 downto 0);
signal secondCount : std_logic_vector(3 downto 0);
signal tenSecCount : std_logic_vector(3 downto 0);
signal controlFlag : std_logic_vector(1 downto 0);
begin
process(reset, clockSource)
begin
if reset = '1' then
hunthsCount <= "0000";
tenthsCount <= "0000";
secondCount <= "0000";
tenSecCount <= "0000";
controlFlag <= "10";
cpldRts <= '1';
elsif microAck = '1' then
cpldRts <= '1';
elsif clockSource'event and clockSource = '1' then
if controlFlag = "00" then
digit <= hunthsCount;
controlFlag <= "01";
cpldRts <= '0';
elsif controlFlag = "01" then
digit <= tenthsCount;
controlFlag <= "10";
cpldRts <= '0';
elsif controlFlag = "10" then
digit <= secondCount;
controlFlag <= "11";
cpldRts <= '0';
elsif controlFlag = "11" then
digit <= tenSecCount;
controlFlag <= "00";
cpldRts <= '0';
if hunthsCount <= "1000" then
hunthsCount <= hunthsCount + "1";
else
hunthsCount <= "0000";
if tenthsCount <= "1000" then
tenthsCount <= tenthsCount + "1";
else
tenthscount <= "0000";
if secondCount <= "1000" then
secondCount <= secondCount + "1";
else
secondCount <= "0000";
if tenSecCount <= "1000" then
tenSecCount <= tenSecCount + "1";
else
tenSecCount <= "0000";
end if;
end if;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
See also:
DigitalSystems.CW2 DigitalSystems.CW2.VHDLTestBench
Categories:
CategoryUni